Low Power Detector Architectures Using On-line Arithmetic for Mobile Communication Receivers

This paper presents low power architectures using conventional and on-line arithmetic to accelerate detection in mobile communication receivers. We identify the potential application of on-line arithmetic for detection in mobile communication systems. We develop innovations in on-line arithmetic modules for better integration with conventional arithmetic systems. We explore a suite of tradeoffs in the usage of on-line arithmetic on the throughput, area and latency and its effects on bit error rate performance. We design novel detector circuits using radix-4 on-line arithmetic for detection algorithms. Our detector can directly interface with conventional arithmetic circuits if necessary and hence, be used as co-processor support to a DSP. A time-constrained conventional arithmetic detector using carry-save adders is first presented that achieves 1.62 1.86 speedup in throughput and a corresponding 1.31 1.08 reduction in area for bit precisions against a direct implementation. The on-line arithmetic detector, however, does much better, providing 3.94 5.94 speedup in throughput and area reduction from 1 14.55 respectively against the same implementation. Hence, by eliminating extraneous computations, decreasing area requirements and simultaneously increasing throughput, on-line arithmetic can provide significant power savings and is well suited for detection in mobile wireless receivers.